1. Field
Exemplary embodiments of the present invention relate to a clock phase adjusting circuit and a semiconductor device including the same.
2. Description of the Related Art
In order for semiconductor devices to exchange a signal (data) at high speed, the semiconductor devices may require a clock for normally recognizing the signal (data), that is, a strobe signal. Thus, when exchanging a signal at high speed, the semiconductor devices also exchange a clock as well as the signal.
FIG. 1 is a block diagram illustrating a configuration to receive data and a clock for strobing the data in a semiconductor device. FIGS. 2A and 2B are timing diagrams illustrating the phases of the data and the clock.
Referring to FIG. 1, data DATA are inputted through a data buffer 101 and then transmitted to a strobing unit 110 through a first path PATH_A. The first path PATH_A may include lines and circuits on a path through which the data DATA inputted through the data buffer 101 are transmitted to the strobing unit 110.
Furthermore, a clock CLK for strobing the data DATA is inputted through a clock buffer 102 and then transmitted to the strobing unit 110 through a second path PATH_B. The second path PATH_B may include lines and circuits on a path through which the clock CLK inputted through the clock buffer 102 is transmitted to the strobing unit 110.
The strobing unit 110 strobes the data DATA transmitted through the first path PATH_A in synchronization with the dock CLK transmitted through the second path PATH_B. The strobed data STROBED_DATA, that is, correctly-recognized data are transmitted to circuits (not illustrated) requiring the data inside the semiconductor device 100.
FIG. 2A illustrates the phases of the data DATA and the clock CLK on the data buffer 101 and the clock buffer 102, respectively. Referring to FIG. 2A, even data D0, D2 and D4 are aligned during logic high level periods of the clock CLK, and odd data D1, D3, and D5 are aligned during logic low level periods of the dock CLK.
FIG. 2B illustrates the phases of the data DATA and the clock CLK at a point 103 and a point 104. Since the data DATA are delayed through the first path PATH_A and the dock CLK is delayed through the second path PATH_B, the phases of the data DATA and the clock CLK deviate from the phases of the data DATA and the clock CLK of FIG. 2A. In order for the strobing unit 110 to recognize the data DATA with a sufficient margin, the edge of the clock CLK is necessary to be positioned at the center of the data DATA. Thus, there is a demand for technique for compensating for a phase difference caused by a path difference between the data DATA and the clock CLK and adjusting the phase of the clock CLK such that the edge of the clock CLK is positioned at the center of the data DATA.